Material engineering for 2D-TMDCs PCC logic devices. (A) Transfer curves of bipolar WSe₂, p-type BP, and n-type MoS₂ transistors. The top-gate voltage V_TG = 0 V, the drain voltage V_DS= 0.5, 0.05, and 0.5 V, respectively. (B) Bipolar WSe₂, p-type BP, and n-type MoS₂ FET can implement XNOR, NOR, and OR logic functions, respectively. (C) Comparison of the number of transistors consumed by different materials, with brown diamonds and blue squares representing MoS₂-based pseudo-NMOS circuits and carbon nanotubes, and red globes representing 2D PCC transistors. (D) Relationship between the thickness of MoS₂ material and the logic function realized by transistors: when the thickness is greater than 4 nm, the logic function is OR, when the MoS₂ thickness is less than 4 nm, the logic function is AND, and using light, the logic function (AND and OR) can be switched. (E) Circuit schematic of a 2T2R-based half adder that utilizes a dual-gate WSe₂ transistor and a MoS₂ transistor interconnected with two fixed-value resistors. (F) The output waveform of the half adder. (A)–(C), (E), (F) Reproduced with permission from [22]. Copyright©2019, Springer Nature. (D) Reproduced with permission from [16]. Copyright©2021, Springer Nature.