Device engineering for 2D-TMDCs-based PCC logic devices. (A) Output characteristic curves of 2D FETs under different polarities. Inset is the schematic band diagram when the semiconductor is in contact with metal. Red represents p-type carrier transport; blue represents n-type carrier transport. (B) Schematic diagram of the WSe₂ transistor based on control gate modulation. (C) CMOS inverter via polarity-controlled gates. Inset: circuit schematic of the inverter. (D) Optical microscope imaging of four transistors forming a logic circuit. (E) Polarity-controllable WSe₂ FETs implemented by NAND, NOR, and XOR output waveforms. (B)–(E) Reproduced with permission from [36]. Copyright©2018, American Chemical Society. (F) Schematic diagram of polarity-controlled WSe₂ FETs based on floating gate structure and different polarities by pulse voltage. Reproduced with permission from [38]. Copyright©2022, Springer Nature. (G) Top: cross-sectional high-resolution transmission electron microscopy image. Bottom: schematic diagram of the dual-gate WSe₂ FETs structure. The drain and source of the device are used as OP command and output ports, and the vertical dual-gate gates are used as logic inputs. With the OP command signal input, a single transistor can perform switchable logic functions. (H) Dual-gate WSe₂ FET for AND logic at a low operating voltage (V_DS=1 V). (I) Dual-gate WSe₂ FETs for XNOR logic at high operating voltage (V_DS=5 V). (G)–(I) Reproduced with permission from [40]. Copyright©2022, Springer Nature.