Circuit architecture design engineering for 2D-TMDCs-based PCC logic device. (A) Schematic diagram of a single transistor with PTL circuit architectures, with the gate used to moderate the channel resistance R_DS and the input signal V_IN able to transfer from the source to the drain. (B) Different R_DS when the FET is in the on-state and off-state. The red curve means transfer logic “1” and the blue curve means transfer logic “0”. (C) AND logic circuit of a PLT circuit based on n-MoS₂ with p-WSe₂ CMOS. Reproduced with permission from [45]. Copyright©2015, American Chemical Society. (D) Circuit diagrams and output waveforms for different logic functions (AND, OR, XNOR). (A), (B), (D) Reproduced with permission from [46]. Copyright©2022, John Wiley and Sons. (E) Comparison of the number of transistors consumed by PTL architecture and pseudo-NMOS to implement different logic functions. (F) Schematic diagram of the ETH device. (G) Seven logic functions implemented based on two ETH devices configured with different logic inputs. (H) Logic single-cell cascade implementing multiplexer, D-locker, 1-full adder, and subtractor logic functions. (F)–(H) Reproduced with permission from [47]. Copyright©2020, Springer Nature.