Structure and electrical properties of the Pt-nanocrystal floating gate memory. (a) Optical image of the nonvolatile flash memory. (b) Transfer curves of the flash memory. A distinct clockwise memory window expands as the back gate voltage increases from ±1 to ±10 V. No obvious hysteresis is observed within a small range of sweeping voltage, indicating negligible interface defect states. (c) Extracted ∆V_th and on-off ratio as a function of the maximum value of the gate voltage. (d) Output characteristic curves at different gate voltages. V_gs increases from 0 to 5 V in increments of 0.5 V. (e) The ultrafast programming test. States 0 and 1 can be achieved by applying a +23 V (20 ns) pulse and −28 V (20 ns) pulse, respectively.