Logic-in-memory operations based on the nonvolatile flash memory. The output voltage is connected to the gate of the pull-up network, and the gates of flash memory are defined as the input terminals (positive voltage pulse as “0” and negative voltage pulse as “1”). (a) Schematic of the fabricated inverter logic device. (b) Circuit diagram of the inverter. (c) Operation of inverter logic with different input pulses. (d) Schematic of the fabricated NAND logic device. (e) Circuit diagram of the NAND device. (f) Operation of NAND logic with different input pulses. (g) Schematic of the fabricated NOR logic device. (h) Circuit diagram of the NOR device. (i) Operation of NOR logic with different input pulses.